1. Field of the Invention
The present invention relates generally to insulator layers formed within integrated circuits. More particularly, the present invention relates to a non-etchback self-aligned method for reducing the sizes of vias formed through insulator layers within integrated circuits.
2. Description of the Related Art
As a consequence of the ever increasing demands for integrated circuit function and performance, advanced generations of integrated circuits have shown a corresponding increase in levels of integration. Some aspects of advanced integrated circuit function and performance demands may be accommodated through increased vertical integration of advanced integrated circuits. Increased vertical integration is accomplished by incorporating additional conductor and interconnect levels within those integrated circuits. However, far greater levels of integrated circuit function and performance increases are typically achieved through increased horizontal integration of advanced integrated circuits. Increased horizontal integration of advanced integrated circuits requires continuing decreases in integrated circuit device dimensions, integrated circuit conductor dimensions and integrated circuit insulator dimensions.
Traditionally, increases in horizontal integration have required corresponding advances in photolithographic and etching processes through which intricate semiconductor features are formed within and/or upon the surfaces of semiconductor substrates. These advances have guided conventional photolithographic methods and materials from exposure wavelengths in the visible and near ultraviolet regions to exposure wavelengths in the deep ultraviolet region. Most recently, these advances have guided advanced photolithographic methods and materials to exposure wavelengths in the x-ray wavelength region.
While the demands for increased integrated circuit functionality and performance will no doubt continue to increase, such increases place a substantial and continuing burden upon the photolithographic and etching processes which are typically employed in forming the integrated circuit devices with the reduced feature sizes that are needed to fulfill the functionality and performance demands. The burden is both technological and economic. It is thus towards the goal of producing advanced integrated circuits having decreased feature sizes without the need for improved photolithographic and etching processes that the present invention is directed.
Methods through which decreased feature sizes within advanced integrated circuits may be achieved without the need for fundamental advances in photolithographic and etching methods are known in the art. For example, Brigham et al., in U.S. Pat. No. 5,342,808 disclose a method for controlling the size of etched vias and metal contacts within insulator layers employed in integrated circuits. The method involves forming a via through an insulator layer by means of standard photolithographic and etching methods. At the bottom of the via is optionally exposed an underlying metal layer. Into the via is then formed a conformal insulator layer which is subsequently anisotropically etched to remove the portion of the insulator layer at the bottom of the via, thus exposing the metal layer. The anisotropic etching leaves residual conformal insulator layer material on the sidewalls of the via. Through the disclosed method there may be provided a via of substantially reduced cross-sectional diameter without need for fundamental advances in photolithographic or etching methods.
Desirable in the art are methods which expand from the disclosure of Brigham et al., and provide additional methods for forming narrow cross-sectional diameter vias through insulator layers within advanced integrated circuits, preferably without the need for fundamental advances in photo lithographic or etching technology. Most desirable are methods which require no additional etching of a narrow cross-sectional diameter via, once formed.